A semiconductor device generally uses several layers of different materials to implement the device properties and function. A layer of material can be conductive, semi-conductive, insulating, resistive, capacitive, or have any number of other properties. Different layers of materials have to be formed using different methods, given the nature of the material, the shape, size or placement of the material, other materials adjacent to the material, and many other considerations.
A Field Effect Transistor (FET) is a semiconductor device that controls the electrical conductivity between a source of electric current (source) and a destination of the electrical current (drain). The FET uses a semiconductor structure called a “gate” to create an electric field, which controls the shape and consequently the electrical conductivity of a channel between the source and the drain. The channel is a charge carrier pathway constructed using a semiconductor material.
Many semiconductor devices are planar, i.e., where the semiconductor structures are fabricated on one plane. A non-planar device is a three-dimensional (3D) device where some of the structures are formed above or below a given plane of fabrication.
A fin-Field Effect Transistor (finFET) is a non-planar device in which a source and a drain are connected using a fin-shaped conducting channel (fin) above the insulator layer. In an FET, a gate has a source-side and a drain-side. Generally, a finFET is fabricated as a multi-gate device in which two or more gates are coupled using one or more fin structures by connecting a drain of one gate to the source of another gate using a fin. For example, a fin of a finFET is usually fabricated between two gates such that the source of one gate is on one side of the fin and the drain of the other gate is on an opposite side of the fin. The direction along the lateral length of the fin running from one gate to the other gate is referred to herein as a lateral running direction of the fin.
A “contact” is an electrically conductive structure formed on an externally accessible surface of a semiconductor device. The semiconductor device, such as an FET, can be electrically connected into a circuit via the contacts. A contact of a semiconductor device electrically couples to one or more structures, generally a single structure, within the semiconductor device. Regardless of the planar or non-planar nature of a semiconductor device, such as the FET, various electrical contacts are generally formed or positioned on a single externally accessible surface of the device for the ease of connecting the device in a circuit.
For example, in a transistor device, one contact connects to the gate structure in the device, one contact connects to the source structure in the device, and one contact connects to the drain structure in the device. Depending on the type of the transistor, additional contacts may be available, e.g., a contact connecting to the fin in a finFET.
A CA contact is an electrical connection that connects to a source/drain (S/D) structure. A CB contact is an electrical connection that connects to a gate structure. A CB contact is fabricated on one surface—usually the top surface (also referred to herein as the frontside) of the device. A circuit external to the finFET uses the CB contact to electrically connect a part of the circuit to a gate in the finFET. The frontside of the finFET is the side opposite to the side of the gate facing the substrate of the device. The side of the gate facing the substrate is referred to herein as the backside of the device.
A TS contact is an electrical contact that provides electrical connectivity to the one or more fins that connect two or more gates to one another. A circuit external to the finFET uses the TS contact to electrically connect a part of the circuit to a fin in the finFET.
A CA contact can be fabricated to electrically couple to the TS contact. However fabricated, the CA contact(s) should be electrically insulated from the CB contact.
For the purposes of the illustrative embodiments, the orientation of the device is described in a three-dimensional space using X, Y, and Z coordinate system. The plane of fabrication is assumed to be the X-Z plane, with vertical structures above the fabrication plane extending in +Y direction and the vertical structures below the fabrication plane extending in −Y direction. This example orientation is not intended to be limiting. From this disclosure, those of ordinary skill in the art will be able to conceive other orientations of semiconductor devices in which an embodiment described herein can be adapted, and such alternate orientations and adaptations are contemplated within the scope of the illustrative embodiments.